TWR-MPC8309【PDF 15/81 页】TOWER SYSTEM MODULE MPC8309

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DDR2 SDRAM

Table 12. DDR2 SDRAM DC electrical characteristics for GV DD (typ) = 1.8 V

Parameter/Condition

I/O supply voltage

I/O reference voltage

I/O termination voltage

Input high voltage

Input low voltage

Output leakage current

Output high current (V OUT = 1.35 V)

Output low current (V OUT = 0.280 V)

Symbol

GV DD

MVREF

V TT

V IH

V IL

I OZ

I OH

I OL

Min

1.7

0.49 × GV DD

MVREF – 0.04

MVREF+ 0.125

–0.3

–9.9

–13.4

13.4

Max

1.9

0.51 × GV DD

MVREF + 0.04

GV DD + 0.3

MVREF – 0.125

9.9

—

—

Unit

V

V

V

V

V

μ A

mA

mA

Note

1

2

3

—

—

4

—

—

Notes:

1. GV DD is expected to be within 50 mV of the DRAM GV DD at all times.

2. MVREF is expected to be equal to 0.5 × GV DD , and to track GV DD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. V TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V ≤ V OUT ≤ GV DD .

Table 13. DDR2 SDRAM capacitance for GV DD (typ) = 1.8 V

Parameter/Condition

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Symbol

C IO

C DIO

Min

6

—

Max

8

0.5

Unit

pF

pF

Note

1

1

Note:

1. This parameter is sampled. GV DD = 1.8 V ± 0.100 V, f = 1 MHz, T A = 25 °C, V OUT = GV DD ÷ 2,

V OUT (peak-to-peak) = 0.2 V.

6.2

DDR2 SDRAM AC electrical characteristics

This section provides the AC electrical characteristics for the DDR2 SDRAM interface.

6.2.1

DDR2 SDRAM input AC timing specifications

This table provides the input AC timing specifications for the DDR2 SDRAM (GV DD (typ) = 1.8 V).

Table 14. DDR2 SDRAM input AC timing specifications for 1.8-V interface

At recommended operating conditions with GV DD of 1.8 V± 100mV.

Parameter

AC input low voltage

AC input high voltage

Symbol

V IL

V IH

Min

—

MVREF + 0.25

Max

MVREF – 0.25

—

Unit

V

V

Note

—

—

The following table provides the input AC timing specifications for the DDR2 SDRAM interface.

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

15

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